“Software-defined buffer/transposer for general matrix multiplication in a programmable IC”
U.S. Patent No. 11,036,827, Jun 2021
Aaron Ng
University of Michigan
Advanced Computer Architecture Lab
M.S.E. Computer Science and Engineering
Hardware Systems, Distributed Computing
Advisor: Igor L. Markov
Advanced Computer Architecture Lab
M.S.E. Computer Science and Engineering
Hardware Systems, Distributed Computing
Advisor: Igor L. Markov
hello@aaron-ng.com
J. Zejda, E. Delaye, Y. Wu, A. N. Ng, A. Sirasao, K. Dao,
“Software-defined buffer/transposer for general matrix multiplication in a programmable IC”
“Software-defined buffer/transposer for general matrix multiplication in a programmable IC”
A. Sirasao, E. Delaye, A. N. Ng, E. Ghasemi,
“Inline image preprocessing for convolution operations using a matrix multiplier on an integrated circuit”
“Inline image preprocessing for convolution operations using a matrix multiplier on an integrated circuit”
U.S. Patent No. 10,460,416, Apr 2021
A. Sirasao, E. Delaye, S. Settle, Z. Ma, E. Ghasemi, X. Teng, A. Ng, J. Zejda
“Software-driven design optimization for fixed-point multiply-accumulate circuitry”
“Software-driven design optimization for fixed-point multiply-accumulate circuitry”
U.S. Patent No. 10,943,039, Mar 2021
L. Liu, Y. Zhou, X. Teng, A. Sirasao, C. Song, A. N. Ng,
“Sparse matrix processing circuitry”
“Sparse matrix processing circuitry”
U.S. Patent No. 10,936,311, Mar 2021
S. Settle, E. Delaye, A. N. Ng, E. Ghasemi, A. Sirasao, X. Teng, J. Zejda,
“Software-driven design optimization for mapping between floating-point and fixed-point multiply accumulators”
“Software-driven design optimization for mapping between floating-point and fixed-point multiply accumulators”
U.S. Patent No. 10,678,509, Jun 2020
A. N. Ng, S. Krishnamurthy, G. S. Gasparyan,
“Timing Closure of Circuit Designs for Integrated Circuits”
“Timing Closure of Circuit Designs for Integrated Circuits”
U.S. Patent No. 10,366,201, Jul 2019
E. Delaye, A. Sirasao, A. N. Ng
“Software-Defined Memory Bandwidth Reduction by Hierarchical Stream Buffering for General Matrix Multiplication In A Programmable IC”
“Software-Defined Memory Bandwidth Reduction by Hierarchical Stream Buffering for General Matrix Multiplication In A Programmable IC”
U.S. Patent No. 10,354,733, Jul 2019
A. N. Ng, E. Delaye, E. Ghasemi, X. Teng, J. Zejda, Y. Wu, S. Settle, A. Sirasao
“Multi-layer neural network processing by a neural network accelerator using host-communicated merged weights and a package of per-layer instructions”
“Multi-layer neural network processing by a neural network accelerator using host-communicated merged weights and a package of per-layer instructions”
U.S. Patent app 5/785,800, Apr 2019
A. N. Ng, J. Zejda, E. Delaye, X. Teng, S. Santan, S. T. Soe, A. Sirasao, E. Ghasemi, S. Settle
“Machine Learning runtime library for neural network acceleration”
“Machine Learning runtime library for neural network acceleration”
U.S. Patent app 15/785,679, Apr 2019
A. N. Ng, E. Delaye, J. Zejda, A. Sirasao
“Host-directed multi-layer neural network processing via per-layer work requests”
“Host-directed multi-layer neural network processing via per-layer work requests”
U.S. Patent app 15/786,102, Apr 2019
A. N. Ng, J. Zejda, E. Delaye, X. Teng, A. Sirasao
“Neural network processing system having host-controlled kernel accelerators”
“Neural network processing system having host-controlled kernel accelerators”
U.S. Patent app 15/786,288, Apr 2019
E. Delaye, A. Sirasao, A. Ng, Y. Wu, J. Zejda
“Image preprocessing for generalized image processing”
“Image preprocessing for generalized image processing”
U.S. Patent app 15/786,267, Apr 2019
X. Teng, A. N. Ng, A. Sirasao, E. Delaye
“Neural network processing system having multiple processors and a neural network accelerator”
“Neural network processing system having multiple processors and a neural network accelerator”
U.S. Patent app 15/785,685, Apr 2019
A. N. Ng, P. Basu, S. Das
“Neural network based Physical Synthesis for Circuit Designs”
“Neural network based Physical Synthesis for Circuit Designs”
U.S. Patent No. 10,192,016, Jan 2019
S. Settle, M. Bollavaram, P. D'Alberto, E. Delaye, O. Fernandez, N. Fraser, A. Ng, A. Sirasao, M. Wu
“Quantizing Convolutional Neural Networks for Low-Power High-Throughput Inference Engines”
“Quantizing Convolutional Neural Networks for Low-Power High-Throughput Inference Engines”
Conference on Neural Information Processing Systems, May 2018
R. Lu, Z. Wang, A. N. Ng, N. Shah, S. Das
“Fanout Optimization to Facilitate Timing Improvement in Circuit Designs”
“Fanout Optimization to Facilitate Timing Improvement in Circuit Designs”
U.S. Patent No. 9,965,581, May 2018
I. Ganusov, A. N. Ng, R. Plyler, S. Das and F. Revenu
“Programmable Integrated Circuit Design Flow using Timing-driven Pipeline Analysis”
“Programmable Integrated Circuit Design Flow using Timing-driven Pipeline Analysis”
U.S. Patent No. 9,836,568, Dec 2017
R. Lu, Z. Wang, A. N. Ng and S. Das
“Post-routing Structural Netlist Optimization for Circuit Designs”
“Post-routing Structural Netlist Optimization for Circuit Designs”
U.S. Patent No. 9,646,126, May 2017
I. Ganusov, H. Fraisse, A. N. Ng, R. T. Possignolo and S. Das,
“Automated Extra Pipeline Analysis of Applications Mapped to Xilinx UltraScale+ FPGAs”
“Automated Extra Pipeline Analysis of Applications Mapped to Xilinx UltraScale+ FPGAs”
Intl. Conference on Field-Programmable Logic and Applications (FPL), August 2016
Q. Wang, A. N. Ng, R. Aggarwal,
“Resource Mapping of Functional Areas on an Integrated Circuit”
“Resource Mapping of Functional Areas on an Integrated Circuit”
U.S. Patent No. 7,840,919, Nov 2010
J. A. Roy, A. N. Ng, R. Aggarwal, V. Ramachandran, and I. L. Markov,
“Solving Modern Mixed-size Placement Instances”
“Solving Modern Mixed-size Placement Instances”
Integration, the VLSI Journal, vol. 42 no. 2, 2009
A. N. Ng, R. Aggarwal, V. Ramachandran and I. L. Markov,
“Solving Hard Instances of Floorplacement,”
“Solving Hard Instances of Floorplacement,”
Intl. Symposium on Physical Design (ISPD), April 2006
M. Moffitt, A. N. Ng and I. L. Markov,
“Constraint-driven Floorplan Repair,”
“Constraint-driven Floorplan Repair,”
Design Automation Conference (DAC), July 2006
J. A. Roy, D. A. Papa, A. N. Ng, I. L Markov,
“Satisfying Whitespace Requirements in Top-down Placement,”
“Satisfying Whitespace Requirements in Top-down Placement,”
Intl. Symposium on Physical Design (ISPD), April 2006
J. A. Roy, D. A. Papa, S. N. Adya, H. H. Chan, J. F. Lu, A. N. Ng, and I. L. Markov,
“Capo: Robust and Scalable Open-Source Min-cut Floorplacer,”
“Capo: Robust and Scalable Open-Source Min-cut Floorplacer,”
Intl. Symposium on Physical Design (ISPD), April 2005
A. N. Ng and I. L. Markov,
“Toward Quality Tools and Tool Flows Through High-Performance Computing,”
“Toward Quality Tools and Tool Flows Through High-Performance Computing,”
Intl. Symposium on Quality Electronic Design (ISQED), March 2005
