“Neural network based Physical Synthesis for Circuit Designs”
U.S. Patent No. 10,192,016, Jan 2019
Aaron Ng
University of Michigan
Advanced Computer Architecture Lab
M.S.E. Computer Science and Engineering
Hardware Systems, Distributed Computing
Advisor: Igor L. Markov
Advanced Computer Architecture Lab
M.S.E. Computer Science and Engineering
Hardware Systems, Distributed Computing
Advisor: Igor L. Markov
hello@aaron-ng.com
A. N. Ng, P. Basu, S. Das,
“Neural network based Physical Synthesis for Circuit Designs”
“Neural network based Physical Synthesis for Circuit Designs”
S. Settle, M. Bollavaram, P. D'Alberto, E. Delaye, O. Fernandez, N. Fraser, A. Ng, A. Sirasao, M. Wu
“Quantizing Convolutional Neural Networks for Low-Power High-Throughput Inference Engines”
“Quantizing Convolutional Neural Networks for Low-Power High-Throughput Inference Engines”
Conference on Neural Information Processing Systems, May 2018
R. Lu, Z. Wang, A. N. Ng, N. Shah, S. Das
“Fanout Optimization to Facilitate Timing Improvement in Circuit Designs”
“Fanout Optimization to Facilitate Timing Improvement in Circuit Designs”
U.S. Patent No. 9,965,581, May 2018
I. Ganusov, A. N. Ng, R. Plyler, S. Das and F. Revenu
“Programmable Integrated Circuit Design Flow using Timing-driven Pipeline Analysis”
“Programmable Integrated Circuit Design Flow using Timing-driven Pipeline Analysis”
U.S. Patent No. 9,836,568, Dec 2017
R. Lu, Z. Wang, A. N. Ng and S. Das
“Post-routing Structural Netlist Optimization for Circuit Designs”
“Post-routing Structural Netlist Optimization for Circuit Designs”
U.S. Patent No. 9,646,126, May 2017
I. Ganusov, H. Fraisse, A. N. Ng, R. T. Possignolo and S. Das,
“Automated Extra Pipeline Analysis of Applications Mapped to Xilinx UltraScale+ FPGAs”
“Automated Extra Pipeline Analysis of Applications Mapped to Xilinx UltraScale+ FPGAs”
Intl. Conference on Field-Programmable Logic and Applications (FPL), August 2016
Q. Wang, A. N. Ng, R. Aggarwal,
“Resource Mapping of Functional Areas on an Integrated Circuit”
“Resource Mapping of Functional Areas on an Integrated Circuit”
U.S. Patent No. 7,840,919, Nov 2010
J. A. Roy, A. N. Ng, R. Aggarwal, V. Ramachandran, and I. L. Markov,
“Solving Modern Mixed-size Placement Instances”
“Solving Modern Mixed-size Placement Instances”
Integration, the VLSI Journal, vol. 42 no. 2, 2009
A. N. Ng, R. Aggarwal, V. Ramachandran and I. L. Markov,
“Solving Hard Instances of Floorplacement,”
“Solving Hard Instances of Floorplacement,”
Intl. Symposium on Physical Design (ISPD), April 2006
M. Moffitt, A. N. Ng and I. L. Markov,
“Constraint-driven Floorplan Repair,”
“Constraint-driven Floorplan Repair,”
Design Automation Conference (DAC), July 2006
J. A. Roy, D. A. Papa, A. N. Ng, I. L Markov,
“Satisfying Whitespace Requirements in Top-down Placement,”
“Satisfying Whitespace Requirements in Top-down Placement,”
Intl. Symposium on Physical Design (ISPD), April 2006
J. A. Roy, D. A. Papa, S. N. Adya, H. H. Chan, J. F. Lu, A. N. Ng, and I. L. Markov,
“Capo: Robust and Scalable Open-Source Min-cut Floorplacer,”
“Capo: Robust and Scalable Open-Source Min-cut Floorplacer,”
Intl. Symposium on Physical Design (ISPD), April 2005
A. N. Ng and I. L. Markov,
“Toward Quality Tools and Tool Flows Through High-Performance Computing,”
“Toward Quality Tools and Tool Flows Through High-Performance Computing,”
Intl. Symposium on Quality Electronic Design (ISQED), March 2005
